Thermal Breakdown of VLSI by ESD Pulses

A first simple, 3-D thermal model is developed to determine the temperature rise and the voltage build-up of VLSI devices subject to the electrical stress of Human-Body Model (HBM) electrostatic discharges (ESD). Specific application of the model to a 1Mb DRAM device yields a failure threshold and a failure site in agreement with the experimental results.