YES (Yield Enhancement Systems) yield model for CMOS IC chips with XYCAL extraction of critical geometrics: Introduction and first applications.

The YES (Yield Enhancement Systems) Yield Model for CMOS IC's is described in detail. The Model has been developed to understand yield quantitatively in terms of physical mechanisms, such as various open-circuits and short-circuits that occur during wafer fabrication. Definitions are given of defect densities per unit length (L sub 0), per unit area (D sub 0), and per unit window (N sub 0). Empirical data on defect densities for each mechanism are obtained from measurements on test structures. The critical geometry for each mechanism for a particular code is extracted from the circuit layout using a new analysis tool named XYCAL for eXtraction for Yield of Critical Areas and Lengths. Then the probability of each mechanism leading to a functional chip is calculated, and the Model or predicted chip yield is calculated from the joint probability function. These four components of the Model (mechanisms, defect densities for each mechanism, critical geometries for each mechanism, calculations) are described.