Yield Model with Critical Geometry Analysis for Yield Projection from Test Sites on a Wafer Basis

A yield model based on test site data and layout analysis of yield-sensitive critical geometries has been developed for a two-level metal, twin-tub 1.25micron CMOS silicon IC process. Electrical test results from the test sites and the critical geometries are used in the model to predict the components of IC chip yield and the total chip functional yield with its statistical confidence interval. An experimental implementation in which test sites and memory chips are fabricated in equal numbers on the same wafer makes it feasible to model the memory chip yield on a wafer-by-wafer basis. The wafer-by-wafer analysis is of interest in cases where there is considerable variation within a lot.