Yswitch: A Multi-Gigabit Packet Switch

The performance of fast packet switches has been limited by the speed of memory components used for buffering packets. Although memory technology continues to improve, the memory bandwidth is expected to remain the bottleneck as networks move to the multi-gigabit range. The switch architecture is a CMOS VLSI chip named Switch Memory. This chip performs switching and buffering of data packets over a wide internal path. By restricting high-speed data movements within the chip boundary, the Switch Memory chip can provide high speed switching and data buffers with a relatively low speed onchip memory. We have built and successfully tested a prototype of the Switch Memory chip. The chip is a building block for a 14x14 packet switch, named Yswitch, with a maximum port speed pf 1 Gigabit/sec. Yswitch has been developed as a part of our overall goal of building a high-speed local area network, named Ynet, which we plan to use as a testbed for experimental research in multi-media networks.