Novel data storage for H.264 motion compensation: system architecture and hardware implementation

Quarter-pel (q-pel) Motion Compensation (MC) is one of the features of H.264/AVC that aids in attaining a much better compression factor than what was possible in preceding standards. The better performance however also brings higher requirements for computational complexity and memory access. This paper describes a novel data storage and the associated addressing scheme, together with the system architecture and FPGA implementation of H.264 q-pel MC. The proposed architecture is suitable for any H.264 standard block size, but also for streams with different image sizes and frame rates. The hardware implementation of a stand alone H.264 q-pel MC on FPGA has shown speeds between 95.9f ps for HD1080p frames, 229f ps for HD 720p and between 2502f ps and 12623f ps for CIF and QCIF format.