In this paper, a novel architecture is proposed to solve the decision feedback equalizer (DFB) critical path problem by parallel processing. This architecture uses the block processing technique.
This paper gives an overview of the effort underway in the ITU-T SG 13 on an architectural framework for QoS support in packet networks, with a focus on IP.
Competition is forcing fundamental changes in the banking industry.
In this paper, we introduce a novel QoS architecture and a measurement-based call admission control algorithm that supports Quality of Service for multiple voice classes.
Link striping algorithms are often used to overcome transmission bottlenecks in computer networks. Traditional striping algorithms suffer from two major disadvantages.
An architecture for system-levl self-test of a wireless communication transceiver integrates the functional (parametric) self-test of the radio frequency (RF) subsystem, and the structural self-tes
Coordination among processes in a distributed system can be rendered very complex in a large-scale system where messages may be delayed or lost and when processes may participate only transiently o
We present a hardware architecture for synthesizing finite state machines (FSM). This architecture is defined at the level of the state transition graph.
Fourth generation mobile networks will allow end-users to roam over different network technologies, such as UMTS, CDMA2000 and Wi-Fi.
VLSI design synthesis is a method for designing hardware that starts with an algorithmic description and uses interactive computer programs to create a finished design.
