We introduce a foveation-based error resilience scheme for low bit rate visual communications over highly error-prone mobile networks.
Scalability, distributivity, interoperability, modularity introduced in cloud computing have deeply changed the legacy data center architecture, implementation and processing capabilities.
We have implemented a same-frequency cellular repeater that uses adaptive signal processing to cancel the feedback path, thereby allowing high gain while maintaining stability.
A fixed-point deep neural network-based equalizer is implemented in FPGA and is shown to outperform MLSE in receiver sensitivity for 50 Gb/s PON downstream link.
We implement rate-adaptable prefix-free code distribution matching in FPGA, demonstrating its real-time feasibility with substantially less hardware resources than low-density parity-check coding.
In this paper, we implement rate-adaptable (RA) prefix-free code distribution matching (PCDM) in a field-programmable gate array (FPGA).
This paper proposes the FPGA implementation of the digit-serial Canonical Signed-Digit (CSD) coefficient FIR filters which can be used as format conversion filters in place of the ones employed for
Boolean satisfiability (SAT) has shown itself to be a promising application for configurable computing and an interesting testbed for new configurable computing compilation techniques.
Real-time computing systems are increasingly used in aerospace and avionic industries.
This paper presents a hardware-accelerated Kvazaar HEVC intra encoder for 4K real-time video coding at up to 120 fps.
