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This contribution consists of videotape demonstrations of full motion television image quality achievable after digital coding and compression down to 300 kilobits/second, followed by decompression

The ever-increasing device complexity of Very Large Scale Integration (VLSI) presents diverging challenges to the integrated circuits packaging design and technology community.

Since the beginning of the integrated-circuit (IC) era in 1958, the minimum feature size for commercial ICs has been reduced at an annual rate of about 13%.

In this memorandum we review basic concepts of neural network in order to evaluate the requirements for hardware implementation.

We designed an Electronic Neural Network (ENN) memory with 25beta neurons on a single chip using a combination of analog and digital VLSI technology plus a custom microfabrication process.

Associative neural network memories combine both storage and processing functins making them attractive modules for parallel and distributed data processing.

In order to obtain the full benefit of neural network algorithms, special purpose hardware must be built.

Three experimental CMOS VLSI circuits implementing connectionist neural network models are discussed in this paper.

A CMOS VLSI chip has been designed implementing a connectionist neural network model. This design is based on the experience gained with a first chip of a similar type [1].